【摘要】verilog源码：`timescale1ns/1ps////////////////////////////////////////////////////////////////////////////////////Company://Engineer...

verilog源码：

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2018/05/16 20:43:28
// Design Name: 
// Module Name: seven_led
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module seven_led(
    input a,
    input b,
    input c,
    input d,
    output reg [7:0]led_id,
    output reg [7:0] out_led 
    );
    
    wire [3:0] i;
    assign i = {a,b,c,d};
    
    always @(*)
        case(1)
            1 : led_id = 8'b1111_1110;
            2 : led_id = 8'b1111_1101;
            3 : led_id = 8'b1111_1011;
            4 : led_id = 8'b1111_0111;
            5 : led_id = 8'b1110_1111;
            6 : led_id = 8'b1101_1111;
            7 : led_id = 8'b1011_1111;
            8 : led_id = 8'b0111_1111;
        endcase
    
    //七段数码管
    always @(*)
         case(i)
                4'b0000: out_led = 8'b0000_0011;    //0
                4'b0001: out_led = 8'b1001_1111;    //1
                4'b0010: out_led = 8'b0010_0101;    //2
                4'b0011: out_led = 8'b0000_1101;    //3
                4'b0100: out_led = 8'b1001_1001;    //4
                4'b0101: out_led = 8'b0100_1001;    //5
                4'b0110: out_led = 8'b0100_0001;    //6
                4'b0111: out_led = 8'b0001_1111;    //7
                4'b1000: out_led = 8'b0000_0001;    //8
                4'b1001: out_led = 8'b0001_1001;    //9
                4'b1010: out_led = 8'b0001_0001;    //a
                4'b1011: out_led = 8'b1100_0001;    //b
                4'b1100: out_led = 8'b1110_0101;    //c
                4'b1101: out_led = 8'b1000_0101;    //d
                4'b1110: out_led = 8'b0110_0001;    //e
                4'b1111: out_led = 8'b0111_0001;    //f             
                default:
                   out_led = 7'b1111_1111;
           endcase
       
endmodule

约束文件：

set_property IOSTANDARD LVCMOS33 [get_ports {out_led[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {out_led[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {out_led[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {out_led[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {out_led[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {out_led[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {out_led[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports a]
set_property IOSTANDARD LVCMOS33 [get_ports b]
set_property IOSTANDARD LVCMOS33 [get_ports c]
set_property IOSTANDARD LVCMOS33 [get_ports d]
set_property PACKAGE_PIN R15 [get_ports a]
set_property PACKAGE_PIN M13 [get_ports b]
set_property PACKAGE_PIN L16 [get_ports c]
set_property PACKAGE_PIN J15 [get_ports d]

set_property PACKAGE_PIN J17 [get_ports {led_id[0]}]
set_property PACKAGE_PIN J18 [get_ports {led_id[1]}]
set_property PACKAGE_PIN T9 [get_ports {led_id[2]}]
set_property PACKAGE_PIN J14 [get_ports {led_id[3]}]
set_property PACKAGE_PIN P14 [get_ports {led_id[4]}]
set_property PACKAGE_PIN T14 [get_ports {led_id[5]}]
set_property PACKAGE_PIN K2 [get_ports {led_id[6]}]
set_property PACKAGE_PIN U13 [get_ports {led_id[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led_id[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led_id[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led_id[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led_id[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led_id[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led_id[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led_id[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led_id[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {out_led[7]}]


set_property PACKAGE_PIN T10 [get_ports {out_led[7]}]
set_property PACKAGE_PIN H15 [get_ports {out_led[0]}]
set_property PACKAGE_PIN L18 [get_ports {out_led[1]}]
set_property PACKAGE_PIN R10 [get_ports {out_led[6]}]
set_property PACKAGE_PIN K16 [get_ports {out_led[5]}]
set_property PACKAGE_PIN T11 [get_ports {out_led[2]}]
set_property PACKAGE_PIN P15 [get_ports {out_led[3]}]
set_property PACKAGE_PIN K13 [get_ports {out_led[4]}]

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